Title :
Automated Timing and Electrical Analysis of a DDR2 Memory Interface
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR
Abstract :
The new IBIS4.1/IEEE1076.1 standard provides the capability to greatly simplify the complex task of electrical and timing analysis of a DDR2 to CPU interface, as well as provides many other productivity enhancing capabilities
Keywords :
IEEE standards; integrated memory circuits; peripheral interfaces; CPU interface; DDR2 memory interface; IBIS4.1/IEEE1076.1 standard; automated timing analysis; electrical analysis; Area measurement; Electronics packaging; Performance analysis; Productivity; Pulse measurements; SPICE; Space vector pulse width modulation; Testing; Timing; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2006 IEEE
Conference_Location :
Scottsdale, AZ
Print_ISBN :
1-4244-0668-4
DOI :
10.1109/EPEP.2006.321202
