Title :
Maximum Tolerable Power Supply Noise for Data-Clock Synchronization
Author :
Kantorovich, Isaac ; Houghton, Chris
Author_Institution :
Intel, Hudson, MA
Abstract :
A new approach to analyze the impact of power supply noise on clock jitter and data-clock synchronization is suggested. Resonances of the worst-case clock jitter and timing margin as functions of supply noise have been demonstrated. Maximum power supply noise that does not violate setup timing constraint is examined
Keywords :
clocks; integrated circuit noise; power supply circuits; synchronisation; timing jitter; clock jitter; data-clock synchronization; power supply noise; timing margin; Clocks; Delay effects; Electronics packaging; Frequency synchronization; Power supplies; Propagation delay; Repeaters; Resonance; Timing jitter; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2006 IEEE
Conference_Location :
Scottsdale, AZ
Print_ISBN :
1-4244-0668-4
DOI :
10.1109/EPEP.2006.321219
