Title :
Sequential logic asynchronous design for CMOS implementation
Author_Institution :
Riga Aviation Univ., Latvia
Abstract :
The method of hazard elimination is adapted for CMOS circuit design. The opportunity of hazard-free CMOS implementation with input inverters is shown. Input variable hazards are avoided by changing one input variable at the time and internal variable hazards-by neighbouring or Tracey´s assignment. The main attention is focused on avoiding hazards between input and internal variables. The internal state assignment to avoid errors caused by this type of hazard is offered
Keywords :
CMOS logic circuits; asynchronous circuits; asynchronous sequential logic; hazards and race conditions; logic design; sequential circuits; state assignment; CMOS circuit design; CMOS implementation; Tracey assignment; hazard elimination method; internal state assignment; neighbouring assignment; sequential logic asynchronous design; CMOS logic circuits; Circuit synthesis; Delay; Hazards; Input variables; Inverters; Logic design; Logic devices; Logic gates; Semiconductor device modeling;
Conference_Titel :
Electrotechnical Conference, 1998. MELECON 98., 9th Mediterranean
Conference_Location :
Tel-Aviv
Print_ISBN :
0-7803-3879-0
DOI :
10.1109/MELCON.1998.692501
