Implementation of high-speed LFSR design with parallel architectures

Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. The contribution of this paper is two fold. First, this paper presents linear transformation of serial LFSR architecture into the transformation of parallel LFSR architecture. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all generator polynomials used in CRC operations and BCH encoders. Second, a new formulation is proposed to modify the parallel LFSR into the form of pipelining and retiming algorithm. We propose a high-speed parallel LFSR architecture based on pipelining and retiming algorithms to reduce the critical path. Finally, we are calculating the Bit Error Rate (BER) tester for the proposed LFSR design. The advantage of this proposed approach over the previous architectures is that it has both feed forward and feedback paths. Also it has the advantage of further increasing the speed-up and it increases the throughput rate. We further propose to apply combined parallel and pipelining techniques to eliminate the fan-out effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. The proposed parallel architecture achieves better area-time product compared to the previous designs.