Finite-difference time-domain on the cell/B.E. processor

Finite-Difference Time-Domain (FDTD) is a kernel used to solve problems in electromagnetics applications such as microwave tomography. It is a data-intensive and computation-intensive problem. However, its computation scheme indicates that an architecture with SIMD support has the potential to bring performance improvement over traditional architectures without SIMD support. The Cell Broadband Engine (Cell/B.E.) processor is an implementation of a heterogeneous multicore architecture. It consists of one conventional microprocessor, PowerPC Processor Element (PPE), and eight SIMD co-processor elements, Synergistic Processor Elements (SPEs). One unique feature of an SPE is that it has 128-entry 128-bit uniform registers which support SIMD. Therefore, FDTD may be mapped well on Cell/B.E. processor. However, each SPE can directly access only 256KB local store (LS) both for instructions and data. The size ofLS is much less than what is needed for an accurate simulation of FDTD which requires large number of fine-grained Yee cells. In this paper, we design the algorithm on Cell/B.E. by efficiently using the asynchronous DMA (direct memory access) mechanism available on an SPE transferring data between its LS and the main memory via the high bandwidth bus on-chip EIB (Element Interconnect Bus). The new algorithm was run on an IBM Blade QS20 blades running at 3.2GHz. For a computation domain of 600 x 600 Yee cells, we achieve an overall speedup of 14.14 over AMD Athlon and 7.05 over AMD Opteron at the processor level.