Design and implementation of a high performance multiplier using HDL

Author

Aparna, P.R. ; Thomas, Nisha

Author_Institution

Dept. of ECE, Lourde Matha Coll. of Sci. & Technol., Kuttichal, India

fYear

2012

Firstpage

1

Lastpage

5

Abstract

This paper presents an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for m × n multiplication where m and n can reach up to 126 bits. Carry Lookahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter. The design entry is done in VHDL and simulated using ModelSim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i targeted towards Spartan 3 FPGA.

Keywords

FIR filters; adders; field programmable gate arrays; hardware description languages; logic design; Mentor Graphics; ModelSim SE 6.4 design suite; Radix-4 Booth multiplier; Radix-8 Booth multiplier; Spartan 3 FPGA; VHDL; Xilinx ISE 9.2i; carry lookahead adder; field programmable gate array; finite impulse response; hardware description language; high performance parallel multiplier; higher order FIR filter; multiplier design; Adders; Algorithm design and analysis; Compressors; Delay; Field programmable gate arrays; Finite impulse response filter; Signal processing algorithms; Booth Encoding; Carry Lookahead Adder; Carry Save Adder; FPGA; HDL; Wallace Tree;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Communication and Applications (ICCCA), 2012 International Conference on

Conference_Location

Dindigul, Tamilnadu

Print_ISBN

978-1-4673-0270-8

Type

conf

DOI

10.1109/ICCCA.2012.6179170

Filename

6179170