DocumentCode
1690966
Title
A Hardware/Software Co-reconfigurable Multimedia Architecture
Author
Jung, Yong Kyu
Author_Institution
Texas A&M Univ., College Station, TX
fYear
2006
Firstpage
73
Lastpage
78
Abstract
The hardware/software co-reconfiguration technique is introduced to design a reconfigurable multimedia architecture that does not employ field-programmable devices. This co-reconfiguration technique does not require modifying existing compilers to retarget their new multimedia processors. This technique allows software developers to rapidly retarget their multimedia processors. In order to present the reconfiguration procedures and performance evaluations of the technique, a smart instruction decoder for Texas Instruments OMAP2420 was implemented and optimized
Keywords
decoding; hardware-software codesign; multimedia systems; reconfigurable architectures; hardware-software coreconfiguration technique; instruction decoder; multimedia architecture; multimedia processor; performance evaluation; Application software; Application specific integrated circuits; Computer architecture; Costs; Decoding; Digital signal processing; Field programmable gate arrays; Hardware; Instruction sets; Multimedia systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Systems for Real Time Multimedia, Proceedings of the 2006 IEEE/ACM/IFIP Workshop on
Conference_Location
Seoul
Print_ISBN
0-7803-9783-5
Type
conf
DOI
10.1109/ESTMED.2006.321277
Filename
4115457
Link To Document