DocumentCode
1690987
Title
Design of an efficient weighted random pattern generation system
Author
Kapur, Rohit ; Patil, Srinivas ; Snethen, Thomas J. ; Williams, T.W.
Author_Institution
IBM Corp. Microelectron, Endicott, NY, USA
fYear
34608
Firstpage
491
Lastpage
500
Abstract
This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided
Keywords
VLSI; automatic test equipment; integrated logic circuits; logic testing; random processes; CMOS; VLSI; burn-out protection; efficient weighted random pattern generation; fault coverage; fault list re-ordering; heuristics; sampling; sorting; weight sets; weighted random patterns; Automatic control; Automatic testing; Circuit faults; Circuit testing; Circuit topology; Electrical fault detection; Fault detection; Linear feedback shift registers; Signal generators; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1994. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2103-0
Type
conf
DOI
10.1109/TEST.1994.527991
Filename
527991
Link To Document