Power optimization of ΔΣ analog-to-digital converters based on slewing and partial settling considerations

A technique to obtain low power ΔΣ ADC designs under slewing and partial settling behavior of the integrators is described. ΔΣ ADCs do not require complete settling of the integrators to the overall converter accuracy due to their oversampling and noise-shaping characteristics. When the slewing and incomplete settling behavior of the modulator are explored properly, it is possible to obtain power optimal designs. Accurate estimates are obtained under non-ideal conditions such as finite switch resistances in the sampling and the feedback paths. It is also shown that the noise reduction strategies such as correlated double sampling (CDS) significantly affect the power requirements