Title :
Power optimization of ΔΣ analog-to-digital converters based on slewing and partial settling considerations
Author :
Naiknaware, Ravindranath ; Fiez, Terri
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
A technique to obtain low power ΔΣ ADC designs under slewing and partial settling behavior of the integrators is described. ΔΣ ADCs do not require complete settling of the integrators to the overall converter accuracy due to their oversampling and noise-shaping characteristics. When the slewing and incomplete settling behavior of the modulator are explored properly, it is possible to obtain power optimal designs. Accurate estimates are obtained under non-ideal conditions such as finite switch resistances in the sampling and the feedback paths. It is also shown that the noise reduction strategies such as correlated double sampling (CDS) significantly affect the power requirements
Keywords :
circuit optimisation; integrating circuits; sigma-delta modulation; ΔΣ analog-to-digital converter; correlated double sampling; integrator; low power design; noise shaping; oversampling; partial settling; power optimization; slewing; switch resistance; Analog-digital conversion; Computer science; Frequency; Noise reduction; Noise shaping; Nonlinear dynamical systems; Operational amplifiers; Power system modeling; Sampling methods; Switches;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.704436
