A novel representation for 3D-LSI floorplan: Merged FT Squeeze

Since semiconductor manufacturing technology has improved, LSIs which consist of several silicon chips (silicon layers) have been put to practical use. Then, signal delay and power consumption are reduced, because wires on different silicon layers are connected each other by bonding wires in the LSI. To reduce signal delay and power consumption further, Through Silicon Via (TSV), which connects wires on adjacent silicon layers as penetration wiring instead of bonding wires, is investigated actively. And it will come into practical use in several years. To make floorplans with considering positions of TSVs, representation of floorplans which implies positional relation of modules on different silicon layers, is required. In this paper, we propose a new representation for three-dimensional floorplans, inspired by FT Squeeze, representation of two-dimensional floor-plans. Effectiveness of the proposed representation is confirmed by experiments.