Title :
A digital hardware architecture for a three-input one-output zero-order ANFIS
Author :
Saldaña, Henry José Block ; Silva-Cárdenas, Carlos
Author_Institution :
Grupo de Microelectron., Pontificia Univ. Catolica del Peru, Lima, Peru
Abstract :
A digital system architecture for a three-input one-output zero-order ANFIS (Adaptive Neuro-Fuzzy Inference System) is presented. The proposed architecture takes into account that the training process is done off-line in the MATLAB environment. The system is implemented as a nonlinear-function generator for test purposes. Post-place and route simulation results obtained on a Xilinx Spartan-3 XC3S200 FPGA are presented. Its correct operation is verified by the results obtained for two chosen functions. These results show that the system is capable of achieving a close approximation of any of the functions with a fast response time.
Keywords :
circuit simulation; field programmable gate arrays; fuzzy neural nets; fuzzy reasoning; MATLAB environment; Xilinx Spartan-3 XC3S200 FPGA; adaptive neuro-fuzzy inference system; digital hardware architecture; digital system architecture; nonlinear-function generator; post-place simulation; route simulation; three-input one-output zero-order ANFIS; training process; Application software; Equations; Field programmable gate arrays; Hardware; Mathematical model; Time factors; Training;
Conference_Titel :
Circuits and Systems (LASCAS), 2012 IEEE Third Latin American Symposium on
Conference_Location :
Playa del Carmen
Print_ISBN :
978-1-4673-1207-3
DOI :
10.1109/LASCAS.2012.6180304
