A low power Successive Approximation A/D converter based on PWM technique

This paper introduces a new architecture for a SAR A/D converter that uses the PWM technique in the internal DAC converter. One of the main disadvantages of traditional SAR ADCs is non-linearity, which degrades the DNL and INL parameters. Those errors are caused by the fabrication process. The proposed architecture aims to eliminate the process mismatches and thus minimizing the errors. In order to validate this architecture, a 4bit A/D converter has been simulated on Spectre simulator using BSIM3v3 model for a 0.5μ CMOS process. The power consumption is only 16μW for a power supply of 2.5V. The sample rate was limited to 200Hz, regarding the circuit design and the maximum frequency achieved by the CMOS process.