A Hardware Accelerator for SAT Solving

The Boolean satisfiability problem (SAT) is a central problem in artificial intelligence, mathematical logic and computing theory with wide range of practical applications. Being an NP-complete problem, the used SAT´s solving algorithm execution time influences the performance of SAT-based applications. FPGAs represent a promising technology for accelerating SAT solvers. In this paper, we present an FPGA-based SAT solver based on depth-first search. Our architecture exploits the fine granularity and massive parallelism of FPGAs to evaluate the SAT formula and perform conflict diagnosis. Conflict diagnosis helps pruning the search space by allowing nonchronological conflict directed backtracking. We compare our SAT solver with three other SAT solvers. The gain in performance is validated through DIMACS benchmarks suite