DocumentCode
1691914
Title
Automatic failure analysis system for high density DRAM
Author
OH, Sang-Chul ; Kim, Jae-Ho ; Choi, Ho-Jeong ; Choi, Si-Don ; Park, Ki-Tae ; Park, Jong-Woo ; Lee, Wha-Joon
Author_Institution
Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
fYear
34608
Firstpage
526
Lastpage
530
Abstract
In this paper, the automatic failure analysis method based on the random bit failure causing the major yield drop in DRAM and the analysis system named “SEC FAILURE ANALYSIS SYSTEM” are discussed. This system is developed for the accurate and rapid electrical analysis of the failure in a statistical manner in order to make a quick feedback to the manufacturing process
Keywords
DRAM chips; automatic testing; failure analysis; fault diagnosis; statistical analysis; automatic failure analysis; electrical analysis; feedback; high density DRAM; random bit failure; test vector generation; yield drop; Automatic testing; Dielectric materials; Dielectric substrates; Failure analysis; Feedback; Manufacturing processes; Material storage; Random access memory; Subthreshold current; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1994. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2103-0
Type
conf
DOI
10.1109/TEST.1994.527995
Filename
527995
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