High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures

Author

Adriaensen, S. ; Dessard, V. ; Delatte, P. ; Querol, I. Rovira ; Flandre, Denis ; Richter, S.

Author_Institution

Microelectron. Lab., Univ. Catholique de Louvain, Belgium

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

79

Lastpage

82

Abstract

High-temperature characterization of a 0.8 μm partially-depleted (PD) silicon-on-insulator (SOI) CMOS process is reported. The process is designed for mixed analog/digital/high-voltage applications. The measurements have been realized on n-MOSFETs, on lateral bipolar transistors and on LDMOS transistors and demonstrate the interest of the process under consideration

Keywords

CMOS integrated circuits; bipolar transistors; high-temperature electronics; leakage currents; power MOSFET; semiconductor device breakdown; semiconductor device measurement; silicon-on-insulator; 0.8 mum; 20 to 300 C; LDMOS transistors; breakdown voltage; high-temperature characterization; lateral bipolar transistors; leakage current; mixed analog/digital/high-voltage applications; n-MOSFETs; on-resistance; partially depleted SOI CMOS process; Bipolar transistors; CMOS process; CMOS technology; Fabrication; Laboratories; MOSFET circuits; Microelectronics; Space technology; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

High Temperature Electronics, 1999. HITEN 99. The Third European Conference on

Conference_Location

Berlin

Print_ISBN

0-7803-5795-7

Type

conf

DOI

10.1109/HITEN.1999.827467

Filename

827467