DocumentCode
1692214
Title
A dual-code-rate memoryless Viterbi decoder for wireless communication systems
Author
Chu Yu ; Yu-Shan Su ; Bor-Shing Lin ; Po-Hsun Cheng ; Sao-Jie Chen
Author_Institution
Dept. of Electron. Eng., Nat. ILan Univ., Yilan, Taiwan
fYear
2013
Firstpage
578
Lastpage
579
Abstract
This paper presents a novel dual-code-rate memoryless Viterbi decoder with a 4-level soft decision for wireless communication systems. Based on the proposed architecture, the survivor memory can be eliminated totally, which will significantly reduce 50% of the total power dissipation. As shown, the proposed design uses approximately 27.5 K gates in 0.18 μm CMOS technology, and its power consumption is approximately 9.8 mW at 80 MHz.
Keywords
CMOS integrated circuits; Viterbi decoding; dual codes; mobile radio; radio networks; software radio; 0.18 μm CMOS technology; 4-level soft decision; SDR; dual-code-rate memoryless Viterbi decoder; frequency 80 MHz; mobile communications; personal communications; power 9.8 mW; power consumption; software defined radio; survivor memory; temperature 27.5 K; total power dissipation; wireless communication systems; Computer architecture; Decoding; Educational institutions; Hardware; Measurement; Viterbi algorithm; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2013 IEEE International Conference on
Conference_Location
Las Vegas, NV
ISSN
2158-3994
Print_ISBN
978-1-4673-1361-2
Type
conf
DOI
10.1109/ICCE.2013.6487025
Filename
6487025
Link To Document