A high PSRR low dropout voltage regulator with fast settling response

Author

Abbasi, Mohammad Usaid ; Bagnall, Darren ; Nagaraju, Vishwas Bangayar

Author_Institution

Dept. of Electron. & Comput. Sci., Univ. of Southampton, Southampton, UK

fYear

2010

Firstpage

183

Lastpage

186

Abstract

A design of a low dropout voltage regulator (LDO) with fast settling response is being reported. This circuit is stable for full load current range from 0 to 150mA. A current boost circuit is being used to improve the transient response. There was an overshoot of mere 10.51mV and settling time achieved was 43.8ns. The PSRR achieved was -84.464dB upto 8.895kHz, and more than -70db till 136.218MHz. The LDO is capable of generating fixed 1V from a supply of 3.0V which on discharging goes to 1.5V. The LDO has been implemented in 0.18μm generic CMOS technology. Simulation result showed that the line regulation achieved was 174.2μV/Vand load regulation was 0.001626%/mA.

Keywords

CMOS integrated circuits; voltage regulators; CMOS technology; LDO; PSRR; current 0 mA to 150 mA; current boost circuit; fast settling response; load current; low dropout voltage regulator; voltage 3 V; Batteries; Logic gates; Regulators; Transient analysis; Transient response; Transistors; Voltage control; Analog circuit design; Fast Transient Response; LDO; line regulation; load regulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Control and Computing Technologies (ICCCCT), 2010 IEEE International Conference on

Conference_Location

Ramanathapuram

Print_ISBN

978-1-4244-7769-2

Type

conf

DOI

10.1109/ICCCCT.2010.5670548

Filename

5670548