Low-on-resistance strain-controlled LDMOS transistors for 0.25-μm power ICs

We have developed a new 12 V LDMOS transistor for 0.25 μm power ICs, which is designed from the viewpoint of mechanical stress to reduce on-resistance. A critically low resistance substrate has been developed to reduce the resistance from the surface source to the backside of the transistor, avoiding compressive stress due to high boron doping in the substrate. A buried-polysilicon sinker is utilized to apply tensile stress to the channel and the offset-drain region. The existing mechanical stress distribution is confirmed by two-dimensional UV-Raman spectroscopy. The transconductance of the LDMOS transistor is increased by 12% owing to the tensile stress and the total on-resistance is reduced by 16% owing to the channel and source resistance reduction, which directly leads to a higher efficiency of analog power circuits.