Title :
Defects, fault coverage, yield and cost, in board manufacturing
Author :
Tegethoff, Mick M V ; Chen, Tom W.
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate component functional defect rate and test coverage. A new yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given
Keywords :
IEEE standards; application specific integrated circuits; circuit optimisation; digital simulation; electronic engineering computing; integrated circuit yield; pattern classification; printed circuit manufacture; printed circuit testing; probability; sensitivity analysis; soldering; surface mount technology; ASIC; Hewlett-Packard; IEEE 1149.1 standard; SMT; Surface Mount Technology; clustering; complex board manufacturing; cost; fault coverage; quality; sensitivity; simulation models; solder defect rate; solder defects; yield; yield model; Assembly; Cost function; Manufacturing processes; Process design; Pulp manufacturing; Sensitivity analysis; Surface-mount technology; Testing; Virtual manufacturing; Yield estimation;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527997
