DocumentCode :
1692378
Title :
Comparison of simultaneous switching noise measurements using netlist compatible multilayer ceramic packages having variously compromised reference planes
Author :
Budell, T. ; Clouser, P. ; Audet, J.
Author_Institution :
IBM Corp., Essex Junction, VT, USA
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Firstpage :
42
Lastpage :
51
Abstract :
This paper presents a comparison of simultaneous switching-output noise and skew measurements taken with a 0.12 μm CMOS test chip on three flip-chip, multilayer-ceramic, single-chip modules (SCMs) having differing amounts of reference mesh and power-supply vias in the package under the chip outline. Missing reference mesh equates to poor current-return paths for signals traversing such package regions. Missing power-supply vias equate to increased supply inductance. The test chip has 732 individually programmable off-chip output buffers, each of which can be individually probed. The first package has full reference mesh under the chip. The second package has reference mesh only in the upper half of the package under the chip. The third package has essentially no reference mesh under the chip. Technology and design features of the chip and package test vehicles are described. Noise and delay measurement techniques and results are presented. The large number of off-chip output buffers enables a statistical view of transmitted noise and skew behavior as signal current-return paths are compromised. This analysis is graphically presented and discussed. Several types of simulations, including extracted loop inductance and full-wave simulation of coupling parameters, are presented. These simulations elucidate the large differences in measured transmitted noise and off-chip output buffer skew between the three packages.
Keywords :
CMOS integrated circuits; buffer circuits; ceramic packaging; circuit simulation; flip-chip devices; integrated circuit design; integrated circuit noise; integrated circuit packaging; integrated circuit testing; reference circuits; 0.12 micron; CMOS test chip; chip design; chip outline; compromised reference planes; coupling parameters; current-return paths; delay measurement techniques; flip-chip multilayer-ceramic single-chip modules; full-wave simulation; loop inductance; netlist compatible multilayer ceramic packages; noise measurement techniques; off-chip output buffer skew; off-chip output buffers; package reference mesh; package test vehicles; power-supply vias; programmable off-chip output buffers; signal current-return paths; simulations; simultaneous switching noise measurements; simultaneous switching-output noise; skew measurements; supply inductance; transmitted noise; Ceramics; Delay; Inductance; Measurement techniques; Noise measurement; Nonhomogeneous media; Packaging; Semiconductor device measurement; Testing; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2002. Proceedings. 52nd
ISSN :
0569-5503
Print_ISBN :
0-7803-7430-4
Type :
conf
DOI :
10.1109/ECTC.2002.1008071
Filename :
1008071
Link To Document :
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