Title :
High-voltage thick layer SOI technology for PDP scan driver IC
Author :
Qiao, Ming ; Jiang, Lingli ; Wang, Meng ; Huang, Yong ; Liao, Hong ; Liang, Tao ; Sun, Zhen ; Zhang, Bo ; Li, Zhaoji ; Huang, Guangzuo ; Zhao, Yuanyuan ; Lai, Li ; Hu, Xi ; Zhuang, Xiang ; Luo, Xiaorong ; Wang, Zhuo
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N+&P+ and a deep P+ are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.
Keywords :
CMOS integrated circuits; driver circuits; electric breakdown; isolation technology; plasma displays; silicon-on-insulator; HV pLDMOS; LV CMOS; PDP scan driver integrated circuit; breakdown voltage; buried oxide layer; deep trench isolation; high-voltage thick layer SOI technology; nLDMOS; nLIGBT; parasitic NPN action; plasma display panels; silicon layer; size 1 mum; size 11 mum; Color; Current measurement; Driver circuits; Integrated circuits; Plasma displays; Silicon; Voltage measurement;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-8425-6
DOI :
10.1109/ISPSD.2011.5890820
