DocumentCode
1692518
Title
Solutions to improve flatness of Id-Vd curves of rugged nLDMOS
Author
Mouhoubi, S. ; Bauwens, F. ; Roig, J. ; Gassot, P. ; Moens, P. ; Tack, M.
Author_Institution
Power Technol. Centre, ON Semicond., Oudenaarde, Belgium
fYear
2011
Firstpage
200
Lastpage
203
Abstract
This work summarizes results of TCAD simulations aiming to reduce/suppress the bump in the output characteristics of rugged nLDMOS devices. It is shown that the origin of the bump is not due to bipolar activation. Thus, by simple variations of the geometrical parameters and/or process variations, the intrinsic MOS of the nLDMOS could be driven in a regime allowing a drastic improvement of its Id-Vd flatness with limited impact on the sRon-Vbd trade-off.
Keywords
MOSFET; technology CAD (electronics); Id-Vd curves; TCAD simulations; bump suppression; intrinsic MOS; rugged nLDMOS devices; Doping; Electric potential; IEEE Potentials; Immune system; Logic gates; Robustness; Semiconductor optical amplifiers;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location
San Diego, CA
ISSN
1943-653X
Print_ISBN
978-1-4244-8425-6
Type
conf
DOI
10.1109/ISPSD.2011.5890825
Filename
5890825
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