Title :
HW/SW architecture for speech recognition acceleration
Author :
Fastow, R. ; Rosner, Sonke ; Natarajan, Vivek ; Hasan, Q. ; Olson, Joe ; Unseld, M. ; Feng Liu ; Chendra, H. ; Bapat, O. ; Chen Liu
Author_Institution :
Spansion, Inc., Sunnyvale, CA, USA
Abstract :
This paper describes a new hardware architecture for fast Acoustic Model scoring in embedded speech recognition systems by integrating an 8-way data-path with a NOR Flash array. This architecture localizes computation of critical algorithms and reduces decode latency and CPU load by 50% for large acoustic models, resulting in lower word error rates for natural language speech recognition.
Keywords :
speech coding; speech recognition; 8-way data-path; CPU load; HW-SW architecture; NOR Flash array; acoustic model; decode latency reduction; embedded speech recognition systems; natural language speech recognition; speech recognition acceleration; word error rates; Acoustics; Bandwidth; Brain modeling; Computational modeling; Computer architecture; Hidden Markov models; Speech recognition;
Conference_Titel :
Consumer Electronics (ICCE), 2013 IEEE International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4673-1361-2
DOI :
10.1109/ICCE.2013.6487038
