DocumentCode :
1692573
Title :
Design of a mixed-signal Cartesian Feedback loop for a low power zero-IF WCDMA transmitter
Author :
Sanaa, W. ; Delaunay, N. ; Le Gal, B. ; Dallet, D. ; Rebai, C. ; Deltimple, N. ; Belot, D. ; Kerherve, E.
Author_Institution :
CIRTA´´COM Res. Lab., Univ. of Carthage, Bizerte, Tunisia
fYear :
2012
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF WCDMA transmitter is presented. The transmitter architecture consists of an analog stage including filters, I/Q modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop. We propose an optimized CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. ASIC synthesis proves that using a not fully pipelined CORDIC architecture allows us to reach 230 MHz with system power consumption under 4.3 mw which is two times less than a fully analog system.
Keywords :
3G mobile communication; application specific integrated circuits; code division multiple access; demodulators; digital arithmetic; feedback; optical transmitters; wavelength division multiplexing; ASIC synthesis; CORDIC architecture; CORDIC design; I/Q modulator; digital-stage design; feedback I/Q demodulator; mixed-signal cartesian feedback loop; third generation wireless communication; transmitter architecture; zero-IF WCDMA transmitter; Application specific integrated circuits; Computer architecture; Multiaccess communication; Radio transmitters; Registers; Spread spectrum communication; Vectors; CORDIC; Mixed-Cartesian feedback loop; WCDMA transmitter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (LASCAS), 2012 IEEE Third Latin American Symposium on
Conference_Location :
Playa del Carmen
Print_ISBN :
978-1-4673-1207-3
Type :
conf
DOI :
10.1109/LASCAS.2012.6180352
Filename :
6180352
Link To Document :
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