Leverages and bottlenecks of MCMs

Summary form only given. The authors discuss the fundamental issues confronting designers and manufacturers of the multichip modules (MCMs). All of them ultimately determine the product cost, be it the in-process and final test yields, the engineering effort in design and manufacturing support, or the MCM quality and reliability. Challenges are compounded in a situation where MCMs are assembled with chips and/or substrates obtained from an outside supplier. Issues range from the design groundrules to the lack of (comprehensive) standards, to the question of responsibility for assurance of quality and reliability, to the profit margins potentially reduced by shipping unpackaged chips. The initial driving force for MCMs has been the improved performance over the SCMs facilitated by the reduced interchip wiring delays. In this decade, all high end mainframes employ MCMs capable of carrying as many as 144 chips and handling up to 4.5 kW. Another driving force is the volume and weight reduction, and the reliability enhancement achievable with silicon-on-silicon MCMs. The growing pinout demand of all but the memory chips pushes the SCM packaging costs beyond those deemed possible with the MCMs