DocumentCode
1692622
Title
Effects of single-electron transistor parameter variations on hybrid circuit design
Author
González, Francisco J Castro ; Reyes, Arturo Sarmiento ; Saenz, Francisco Javier Zamudio
fYear
2012
Firstpage
1
Lastpage
4
Abstract
A behavioral model for the single-electron transistor (SET) that includes variations for the tunneling resistance is introduced. The resulting model is recast in a closed analytical form that expresses the characteristics of the single-electron transistor and it is implemented in a Verilog-A module to be used in hybrid simulation of MOS-SET circuits. Model generation has been achieved by using a piecewise linear techniques.
Keywords
piecewise linear techniques; semiconductor device models; single electron transistors; tunnelling; MOS-SET circuits; Verilog-A module; behavioral model; hybrid circuit design; model generation; parameter variations; piecewise linear techniques; single-electron transistor; tunneling resistance; Analytical models; Equations; Integrated circuit modeling; Inverters; Mathematical model; Resistance; Single electron transistors; Hybrid Simulation; Piecewise-Linear modeling; Single-Electron Transistor;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (LASCAS), 2012 IEEE Third Latin American Symposium on
Conference_Location
Playa del Carmen
Print_ISBN
978-1-4673-1207-3
Type
conf
DOI
10.1109/LASCAS.2012.6180354
Filename
6180354
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