• DocumentCode
    1692632
  • Title

    Flip chip organic substrate with metal column

  • Author

    Lan, James J D ; Chang, Jeff ; Lu, Peter ; Chen, Kevin ; Wang, Yu-Po ; Yang, Abe-JM

  • Author_Institution
    Kinsus Corp., Santa Clara, CA, USA
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    95
  • Lastpage
    99
  • Abstract
    Discusses the issue of stress induced from CTE mismatch between silicon and organic substrate in a flip-chip package. Although the use of underfill has greatly reduced the stress on the solder bump under die by holding the stretched substrate to silicon, the solder joints are still seeing high stress prior to the process. The flatness of the assembly becomes an issue with the stretched substrate after the underfilled epoxy gets cured. This situation will get worse with large die size. It is not uncommon to see a flip chip size greater than 20 mm. In this paper metal columns are built on the substrate instead of silicon using the existing PCB process. They are imbedded in a layer of low modulus epoxy. It forms a metal column matrix and provides a mechanical cushion for the stress to be generated after the flip chip attachment and solder reflow. The structure of the metal column was disclosed and finite element analysis was performed as the simulated mechanical analysis to quantify the improvement of stress on the die and warpage after flip chip solder bump reflow and after underfill epoxy curing. The impact of following material selections and/or properties is analyzed and conclusions drawn: 1. Matrix epoxy with different modulus 2. Thickness of matrix epoxy and height of metal column 3. Material of metal column.
  • Keywords
    ball grid arrays; finite element analysis; flip-chip devices; integrated circuit packaging; reflow soldering; thermal expansion; CTE mismatch; ball grid arrays; die size; finite element analysis; flip chip organic substrate; flip-chip package; low modulus epoxy; matrix epoxy thickness; metal column; simulated mechanical analysis; solder joints; solder reflow; Analytical models; Assembly; Finite element methods; Flip chip; Packaging; Performance analysis; Silicon; Soldering; Stress; Transmission line matrix methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2002. Proceedings. 52nd
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-7430-4
  • Type

    conf

  • DOI
    10.1109/ECTC.2002.1008079
  • Filename
    1008079