DocumentCode :
1693660
Title :
Associative digital neural network based on code and graph theories
Author :
Tanaka, Mamoru ; Takeya, Kazutoshi ; Kanaya, Mitsuhisa ; Chigusa, Yasutami
Author_Institution :
Dept. of Electr. & Electron. Eng., Sophia Univ., Tokyo, Japan
fYear :
1989
Firstpage :
2193
Abstract :
An associative DNN (digital neural network) called SANNET, which is based on code and graph theories, is presented. Each neuron is an exclusive-OR unit. In the learning process, all node syndromes from all neurons are constrained to be zero, and a binary `current´ code that expresses a loop on each subnetwork is generated on the basis of the orthogonality of loops and cutsets. Only information on the tree is stored in each subnetwork. In the associative process, the incomplete code on the cotree of each subnetwork is corrected to the complete code according to the error-correcting capacity. SANNET has structural redundancy, sparsity, cellular structure, high concurrency, variable code length, robustness, testability, reliability, logical neurons, unions of logic and storage elements, no crosstalk, high speed, and a unique solution. The SANNET can be fabricated as a CMOS gate array. It can be applied to recognition and classification in which the recognized items are expressed by feature vectors with different lengths. Some simulation results for pattern completion are given
Keywords :
CMOS integrated circuits; cellular arrays; computerised pattern recognition; graph theory; learning systems; logic arrays; neural nets; redundancy; CMOS gate array; SANNET; associative digital neural network; cellular structure; classification; code theory; error-correcting capacity; exclusive-OR unit; feature vectors; graph theory; high concurrency; high speed; learning process; logic/storage elements union; logical neurons; neurons; node syndromes; pattern completion; recognition; reliability; robustness; sparsity; structural redundancy; testability; unions; variable code length; CMOS logic circuits; Concurrent computing; Crosstalk; Error correction codes; Graph theory; Logic testing; Neural networks; Neurons; Redundancy; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
Type :
conf
DOI :
10.1109/ISCAS.1989.100812
Filename :
100812
Link To Document :
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