• DocumentCode
    169382
  • Title

    Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level

  • Author

    Thangaraju, Sara ; England, Luke ; Rabie, Mohamed ; Zhang, Dejing ; Kumarapuram, G. ; McGowan, R. ; Selsley, A. ; Giridharan, R.R. ; Gu, Sijia ; Seshachalam, V. ; Wang, Chingyue ; Kakita, S. ; Baral, S. ; Kim, Wonhee ; Edmundson, H.

  • Author_Institution
    GLOBALFOUNDRIES, Malta, NY, USA
  • fYear
    2014
  • fDate
    19-21 May 2014
  • Firstpage
    51
  • Lastpage
    56
  • Abstract
    This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3μm top entrant critical dimension (CD) and 50μm depth. Higher AR TSV integration is explored due to the lower stress influence of TSVs observed in adjacent CMOS devices.
  • Keywords
    CMOS integrated circuits; three-dimensional integrated circuits; vias; CMOS device; high aspect ratio via middle; size 3 mum; size 50 mum; through silicon vias; top entrant critical dimension; void free gap fill; Delamination; Resists; Silicon; Standards; Stress; Through-silicon vias; 3D; KOZ; TSV;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI
  • Conference_Location
    Saratoga Springs, NY
  • Type

    conf

  • DOI
    10.1109/ASMC.2014.6846976
  • Filename
    6846976
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=169382