Correlation study Of spatial ESC temperature profile and optical CD/CD SEM measurements to investigate silicon recess and gate CD after etch

The gate module comprises arguably some of the most critical process steps in 28nm semiconductor device manufacturing. One key step involved is the final gates etch. Typically all chip manufacturers dedicate a large part of their metrology capacity to the control of related device-limiting process steps. Most importantly the gate length at the bottom of the polysilicon line needs to be controlled very tightly. But given the challenging requirements in carrier density engineering more and more attention is paid to the area located next to the actual gate line. The etch process if not very well monitored and controlled can cause loss of active silicon very often denominated as a recess into the silicon. A loss of material even in the Angstrom range will affect device performance. Should this step be out of specification, it will adversely affect saturation drive current (I_{D SAT}) by reducing the charge carrier density in source and drain regions, leading to degraded device performance [1]. Finding a root cause for silicon recess problems, especially in the preceding etch step, has previously proved difficult due to the numerous influences involved during the etch process. However one major influence, electrostatic chuck (ESC) temperature, is now possible to measure using KLA-Tencor´s SensArray product. The ESC temperature is shown as a temperature profile across the 300mm SensArray wafer. The 65 temperature sensors allow for high resolution intra sensor interpolation. This paper discusses a silicon recess/gate critical dimension (CD) problems after gate etch, which were detected using a KLATencor optical CD metrology tool with latest generation spectroscopic critical dimension (SCD) software, an Applied Materials´ CD SEM tool, and overlaying the measurement profiles against a SensArray temperature profile, from the same etch chamber. The results revealed a strong correlation to temperature gradients. Increasing ESC monitoring in critical etch chambers usi- g the SensArray wafer could potentially reduce the Si recess and gate CD problem, leading to a greater number of high performing gates.