Title :
Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O
Author :
Van der Linden, J. Th ; Konijnenburg, M.H. ; van de Goor, A.J.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
Industrial circuit designs commonly contain three-state elements, such as buses and drivers, transmission gates, and bidirectional I/O. A 5-valued fast fault simulation method and a 4-valued parallel pattern version that can handle these circuits are presented. Results demonstrate the effectiveness of the proposed methods in the presence of three-state elements, and show but a small performance degradation compared to 2- or 3-valued fault simulation
Keywords :
automatic testing; design for testability; digital simulation; electronic engineering computing; fault diagnosis; integrated circuit testing; logic testing; ATPG; bidirectional I/O; bus patch procedure; criticality; fast fault simulation; five-valued fast fault simulation; four-valued parallel pattern; industrial digital circuit design; performance degradation; three-state circuits; three-state elements; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Computational modeling; Concurrent computing; Encoding; Logic circuits; Logic testing;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.528005
