A quantified safety analysis for Safety Fuzzy Logic Controller 1002 reliability block diagrams

This paper describes an analytical study to quantify the safety integrity of a Safety Fuzzy Logic Controller (SFLC) implemented in Field Programmable Gate Array (FPGA). In the area of the security of complex electronic systems, new Safety Standards as IEC 61508 occur and are designed to quantify the probability of dangerous failure (PFD) of a hardware failure of a system. The safety analyses addresses system architecture, hardware failure probability, diagnostic coverage factors and proof test interval. This quantification allows assignment of a Safety Integrity Level to a SFLC and will be taken, in consequence, of process hazard and risk analysis. This paper recalls the concepts of reliability block diagrams useful for calculating the probability of dangerous failure, including an explanation of the different parameters involved in the calculation.