DocumentCode
169480
Title
Quasi-primitive block-wise concatenated BCH codes for NAND flash memories
Author
Daesung Kim ; Jeongseok Ha
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
fYear
2014
fDate
2-5 Nov. 2014
Firstpage
611
Lastpage
615
Abstract
In this work, we consider high-rate error-control systems based on block-wise concatenated Bose-Chaudhuri-Hocquenghem (BC-BCH) codes with iterative hard-decision decoding (IHDD) for storage devices using multi-level per cell (MLC) NAND flash memories. In particular, we propose a novel design rule of BC-BCH codes which consists of quasi-primitive BCH codes and block-wise concatenation of the constituent codes. Comprehensive performance comparisons are carried out among error-control systems with various coding schemes such as BC-BCH codes and LDPC codes.
Keywords
BCH codes; NAND circuits; concatenated codes; error correction codes; flash memories; BC-BCH codes; IHDD; MLC NAND flash memories; block-wise concatenated Bose-Chaudhuri-Hocquenghem codes; high-rate error-control systems; iterative hard-decision decoding; multilevel per cell NAND flash memories; quasiprimitive block-wise concatenated BCH codes; Ash; Bit error rate; Complexity theory; Decoding; Iterative decoding; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory Workshop (ITW), 2014 IEEE
Conference_Location
Hobart, TAS
ISSN
1662-9019
Type
conf
DOI
10.1109/ITW.2014.6970904
Filename
6970904
Link To Document