DocumentCode :
1694926
Title :
Keynote Speech 2
Author :
Renovell, M.
Author_Institution :
LIRMM, France
fYear :
2009
Abstract :
With today manufacturing technology, it is not possible to eliminate all defects so that every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. In this situation, the test process consists in identifying defective circuits by applying test vectors in such a way that the presence of the defect can be observed on some circuit outputs. Traditionally, test generation targets on fault models to produce tests that are expected to identify defects such as unintended shorts and opens. Test generation does not directly target defects for two main reasons. Firstly, many defects are not easy to analyze and no model exists to completely describe their behavior, thus making inconsistent test generation for these defects. Secondly, there can be a very large number of possible defects in a circuit. Since test generation and test application are limited by available resources such as memory and time, generating tests for all defects is unfeasible. Consequently, a relatively small set of abstract defects, namely faults, is constructed and these faults are targeted to generate the tests. With this approach, the test quality relies on fortuitous detection of non-targeted defects. As the quality demands increase, the effectiveness of test generation without any defect consideration becomes questionable. High quality test generation requires a better knowledge of defect behavior. As a matter of fact, the analysis of defect behavior is a quite difficult task. One of the main difficulties comes from the presence of random value parameters in the defects, preventing any prediction of the defect behavior. The mechanisms of defect appearance are obviously not controlled, resulting in electrical situations with unknown parameters. As a simple example, how to predict the voltage created by a shortcircuit when the value of the short resistance is not known a priori. The classical assumptions such as zero-resista- ce short can no longer be used and a realistic analysis of defect behavior is required. A challenging but realistic model of defect behavior must now incorporate the random parameters. In the following different fault models for resistive bridging are revisited.
Keywords :
integrated circuit manufacture; integrated circuit testing; defect-model oriented testing; defective circuit identification; fault-model; manufacturing technology; shortcircuit; test generation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Technology, Design, and Testing, 2009. MTDT '09. IEEE International Workshop on
Conference_Location :
Hsinchu
Print_ISBN :
978-0-7695-3797-9
Type :
conf
DOI :
10.1109/MTDT.2009.10
Filename :
5280066
Link To Document :
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