DocumentCode :
1695054
Title :
Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS
Author :
Tran, Anh T. ; Baas, Bevan M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California - Davis, Davis, CA, USA
fYear :
2010
Firstpage :
87
Lastpage :
91
Abstract :
Low-power circuits is quickly increasing their importance due to the high cost in design of cooling systems with complex chip packaging techniques, and also due to the low energy consumption requirement of portable devices powered by a limited battery capacity. This paper presents design of a low-power 32-bit adder that is a basic functional unit in most computational platforms. Its energy efficiency is highly achieved while operating in the subthreshold regime. Simulation results in 45-nm PTM CMOS show the adder consumes only 22 fJ per computation at 0.2 V with maximum operating frequency of 3.8 MHz. While targeting an acceptable frequency of 100 MHz, it consumes only 3.4 μW or 34 fJ per computation at 0.37 V. At 1.0 V, it can operate at up to 2.85 GHz while consuming only 735 μW or 257 fJ per computation. It also stably operates at only 0.1 V with throughput of 400 kHz and consumes 18 nW.
Keywords :
CMOS digital integrated circuits; adders; integrated circuit design; integrated circuit modelling; low-power electronics; PTM CMOS simulation; energy 22 fJ; energy 257 fJ; energy 34 fJ; energy efficiency; energy-efficient 32-bit adder design; frequency 100 MHz; frequency 2.85 GHz; frequency 3.8 MHz; frequency 400 kHz; low-power circuits; power 18 nW; power 3.4 muW; power 735 muW; size 45 nm; subthreshold voltage; voltage 0.1 V; voltage 0.2 V; voltage 0.37 V; voltage 1.0 V;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications and Electronics (ICCE), 2010 Third International Conference on
Conference_Location :
Nha Trang
Print_ISBN :
978-1-4244-7055-6
Type :
conf
DOI :
10.1109/ICCE.2010.5670687
Filename :
5670687
Link To Document :
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