Title :
A VLSI implementation of multi-layer neural network with ternary activation functions and limited integer weights
Author :
Hoskins, B.G. ; Haskard, M.R. ; Curkowicz, G.R.
Author_Institution :
Sch. of Electron. Eng., Univ. of South Australia, The Levels, SA, Australia
Abstract :
This paper describes a digital neural network architecture and its VLSI implementation. Multi-layer neural networks are made feasible through input and output signal multiplexing, ternary quantisation of signals and integer weights. Use of the chip is demonstrated in the simulation of a character recognition problem
Keywords :
CMOS digital integrated circuits; VLSI; character recognition; learning (artificial intelligence); neural chips; neural net architecture; parallel architectures; VLSI implementation; character recognition problem; digital neural network architecture; limited integer weights; multilayer neural network; signal multiplexing; ternary activation functions; ternary quantisation; Application software; Artificial neural networks; Character recognition; Floating-point arithmetic; Hardware; Intelligent networks; Multi-layer neural network; Neural networks; Quantization; Very large scale integration;
Conference_Titel :
Microelectronics, 1995. Proceedings., 1995 20th International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-2786-1
DOI :
10.1109/ICMEL.1995.500978
