A paradigm for massively parallel cellular architectures

This paper starts from the paradigm of the LATTICE architecture developed at Purdue University in the 80´s, and goes one step beyond in making the hardware platform as uniform as possible, which results in the introduction of a new paradigm, referred to here as the HONEYCOMB architecture. The LATTICE architecture deals with only two types of architectural elements: for processor/memory activities, and for data communications. The HONEYCOMB architecture deals with only one type of architectural element: an element that can be internally reconfigured to serve as either a processing element, or a memory cell, or an element of a data communications bus. This paper gives the basic rationales of the HONEYCOMB architecture, and demonstrates its usage in one highly demanding application. Also, the paper describes one possible mapping methodology for transforming an algorithm that is suitable for this type of uniform architecture