A Low-Complexity Reed-Solomon Decoder

A new low-complexity Reed-Solomon decoder is presented in this paper. The proposed RS decoder features a novel time-sharing scheme of decoding elements, and thus a low complexity for hardware implementation. After existing RS decoding algorithms are investigated, the algorithms with lower complexities are introduced in the decoder. The regular architecture for inversion-free Berlekamp-Massey algorithm of finding the error-locator polynomial is employed and further exploited for computing syndromes and determining the error pattern, two other phases of RS decoding. As shown in synthesis results, the FPGA resource is reduced by about 75% in contrast to that of the conventional decoder. Attaining significant reduction of hardware complexity, the proposed decoding architecture is competent for efficiency-demanding systems, in particular for wireless and mobile communication systems.