Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-chip Cache

Technology scaling is increasingly yielding diminishing returns in terms of product performance, power, and its yield. Recent development in through-silicon via (TSV) technology has made multi-layer stacking (or 3D integration) a viable solution, opening possibility for coping with the issues related to poor interconnect scaling trend. In this direction there have been research works looking separately at performance, power, and area (or cost) benefits associated with the shift from 2D to 3D manufacturing process for SRAM. However, the poor scaling trend associated with devices still remains as a challenge in realizing large on-chip memories. Heterogeneous 3D integration has been widely adopted for bringing analog, RF, MEMS, DRAM, SRAM, among other wide application on a single chip. In this work, we propose to use heterogeneous 3D integration as an alternative means to manufacture SRAM with multiple technologies. This choice expands the design space that a SRAM designer has thus allowing graceful management of issues related to technology scaling. The main roadblock in realizing 3D integration is the manufacturing cost associated with the TSV process and its yield. Additionally, increased thermal congestion between 3D layers can potentially accelerate many of the reliability mechanisms (gate oxide degradation like negative bias temperature instability (NBTI)) bringing down the SRAM lifetime yield. Hence to help the system designer understand the overall benefit an integrated on-chip cache analysis flow is implemented to assess the shift from planar to 3D SRAM design under one platform. Our study shows performance, power, cost, and lifetime yield benefit in the move towards heterogeneous 3D cache compared with 2D caches and homogeneous 3D caches.