Title :
Reliability assessment of flipchip on build up laminate based multi-chip package
Author :
Chai, T.C. ; Lee, Charles ; Ma, Y.Y. ; Wong, E.H. ; Zhang, X.W. ; Pinjala, D. ; Murthy, S.S. ; Teo, P.S.
Author_Institution :
Inst. of Microelectron., Singapore, Singapore
fDate :
6/24/1905 12:00:00 AM
Abstract :
A high performance multi-chip package with ∼1300 I/O have been developed. This prototype package uses a build up (BU) laminate substrate with laser-drilled blind vias to provide the high density interconnections for substrate level integration as well as high I/O routing for the 2nd level interconnection to the PCB. Chip to substrate interconnection is by means of flipchip bonding and BGA solder ball for board attach. This paper describes the initial evaluation of reliability testing for the package with emphasis on microvia interconnection reliability and discusses the failure modes encountered with the multi-chip package.
Keywords :
chip-on-board packaging; failure analysis; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; laminates; laser beam machining; microassembling; multichip modules; soldering; BGA solder ball board attach; I/O routing; PCB level interconnection; build up laminate substrate; chip to substrate interconnection; failure modes; flipchip bonding; flipchip on build up laminate based multi-chip package; high density interconnections; laser-drilled blind via; microvia interconnection reliability; multi-chip package; package reliability test; prototype package; reliability assessment; substrate level integration; Bonding; Chemical technology; Consumer electronics; Dielectric substrates; Electronic packaging thermal management; Electronics packaging; Laminates; Microelectronics; Routing; Testing;
Conference_Titel :
Electronic Components and Technology Conference, 2002. Proceedings. 52nd
Print_ISBN :
0-7803-7430-4
DOI :
10.1109/ECTC.2002.1008181
