Analogue fault simulation based on layout dependent fault models

Author

Harvey, R.J.A. ; Richardson, A.M.D. ; Bruls, E.M.J.G. ; Baker, K.

Author_Institution

Dept. of Eng., Lancaster Univ., UK

fYear

34608

Firstpage

641

Lastpage

649

Abstract

A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be improved by the use of a supplementary test based on power supply variations

Keywords

analogue integrated circuits; automatic testing; circuit analysis computing; fault diagnosis; integrated circuit layout; integrated circuit testing; mixed analogue-digital integrated circuits; phase locked loops; VLSI; analogue fault simulation; behavioural models; complex analogue circuits; fault coverage; layout dependent fault models; mixed-signal phase locked loop circuit; power supply variations; process defect statistics; production test; supplementary test; testability analysis; Circuit faults; Circuit simulation; Circuit testing; Laboratories; Low voltage; Phase locked loops; Power supplies; Production; Statistical analysis; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1994. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2103-0

Type

conf

DOI

10.1109/TEST.1994.528009

Filename

528009