Title :
Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors
Author :
Zhao, Peiyi ; McNeely, Jason ; Golconda, Pradeep ; Bayoumi, Magdy A. ; Barcenas, B. ; Hu, Jianping
Author_Institution :
Chapman Univ., Orange, CA
Abstract :
In this paper, a new technique for implementing low energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch shared (CBS) scheme to reduce the number of clocked transistors in the design. As compared to the other state of the art double-edge triggered flip- flop designs, the newly proposed CBSip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively.
Keywords :
clocks; flip-flops; low-power electronics; transistors; clock branch shared scheme; clocked transistor; double-edge triggered flip-flop; low power design; Art; Batteries; Clocks; Energy consumption; Flip-flops; Frequency; Latches; Pulse generation; Threshold voltage; Timing;
Conference_Titel :
Circuits and Systems for Communications, 2008. ICCSC 2008. 4th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-1707-0
Electronic_ISBN :
978-1-4244-1708-7
DOI :
10.1109/ICCSC.2008.80
