DocumentCode
1695710
Title
Performance estimation in a simultaneous multithreading processor
Author
Serrano, Mauricio J.
Author_Institution
Santa Teresa Lab., IBM Corp., San Jose, CA, USA
fYear
1996
Firstpage
97
Lastpage
101
Abstract
We present a model to estimate the performance of dynamically interleaving instruction streams in super-scalar architectures. Instructions executed per cycle (IPC) are calculated from simple descriptions of the workload and hardware. We compare estimates for several programs against results from a simulator
Keywords
computer architecture; performance evaluation; pipeline processing; virtual machines; dynamically interleaving instruction streams; hardware; instructions executed per cycle; performance estimation; programs; simulator; simultaneous multithreading processor; super-scalar architectures; workload; Analytical models; Costs; Electronic mail; Hardware; Hazards; Interleaved codes; Laboratories; Multithreading; Throughput; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1996. MASCOTS '96., Proceedings of the Fourth International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-7235-8
Type
conf
DOI
10.1109/MASCOT.1996.501000
Filename
501000
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