Design of CML Ring Oscillators With Low Supply Sensitivity

The causes of supply noise-induced frequency variation in CML ring oscillators are investigated and a novel circuit topology that reduces the supply sensitivity is presented. It is shown that this technique causes only a slight reduction in the maximum oscillation frequency and maintains nearly the same random jitter generation while greatly reducing the sinusoidal jitter caused by power supply variation. Measurement results from a prototype chip fabricated in 0.18 μm CMOS process verify the effectiveness of the proposed technique.