Design of CML Ring Oscillators With Low Supply Sensitivity

Author

Xiaoyan Gui ; Green, Michael M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA

Volume

60

Issue

7

fYear

2013

fDate

Jul-13

Firstpage

1753

Lastpage

1763

Abstract

The causes of supply noise-induced frequency variation in CML ring oscillators are investigated and a novel circuit topology that reduces the supply sensitivity is presented. It is shown that this technique causes only a slight reduction in the maximum oscillation frequency and maintains nearly the same random jitter generation while greatly reducing the sinusoidal jitter caused by power supply variation. Measurement results from a prototype chip fabricated in 0.18 μm CMOS process verify the effectiveness of the proposed technique.

Keywords

CMOS integrated circuits; integrated circuit noise; jitter; low-power electronics; network topology; oscillators; random processes; CML ring oscillator; CMOS process; circuit topology; low supply sensitivity; maximum oscillation frequency; power supply variation; random jitter generation; sinusoidal jitter; size 0.18 mum; supply noise-induced frequency variation; Current mode logic (CML); periodic jitter; supply sensitivity; voltage-controlled oscillator (VCO);

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2012.2230583

Filename

6497079