Title :
The design and simulation of the PACE prototype architecture
Author :
Ieromnimon, F.Z. ; Reynolds, T.J. ; Waite, M.E.
Author_Institution :
Dept. of Comput. Sci., Essex Univ., Colchester, UK
Abstract :
We present a case study of the use of a Unix/C/Verilog production environment to aid the design, from concept to physical prototype, of the PACE parallel graph rewriting architecture. The entire architecture has been modelled, so that simulated runs of complete programs are possible. The architecture´s model is currently being refined towards a component by component detailed hardware design
Keywords :
Unix; distributed memory systems; graph theory; parallel architectures; virtual machines; PACE parallel graph rewriting architecture; PACE prototype architecture design; PACE prototype architecture simulation; Unix/C/Verilog production environment; architecture modelling; complete programs; component by component detailed hardware design; simulated runs; Computational modeling; Computer architecture; Computer science; Hardware; Processor scheduling; Production; Prototypes; Virtual prototyping; Yarn;
Conference_Titel :
Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1996. MASCOTS '96., Proceedings of the Fourth International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-7235-8
DOI :
10.1109/MASCOT.1996.501010
