DocumentCode
1696166
Title
Design and optimization of a novel compliant off-chip interconnect One-Turn Helix
Author
Zhu, Qi ; Ma, Lunyu ; Sitaraman, Suresh K.
Author_Institution
Comput.-Aided Simulation of Packaging Reliability Lab., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
910
Lastpage
914
Abstract
As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. A novel compliant off-chip interconnect, One-Turn Helix (OTH), is designed as an underfill-free interconnect. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beam with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.
Keywords
chip scale packaging; circuit optimisation; compliance control; finite element analysis; integrated circuit design; integrated circuit interconnections; FEA; IC design; IC fabrication; compliant interconnects; electrical performance; mechanical performance; off-chip interconnect; one-turn helix; optimization; organic substrate; reliability; response surface methodology; silicon die; thermal expansion mismatch; underfill-free interconnect; wafer-level packaging; Costs; Design optimization; Electronic packaging thermal management; Electronics packaging; Fabrication; Geometry; Integrated circuit packaging; Silicon; Thermal expansion; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2002. Proceedings. 52nd
ISSN
0569-5503
Print_ISBN
0-7803-7430-4
Type
conf
DOI
10.1109/ECTC.2002.1008208
Filename
1008208
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