A digital phase-locked loop with a fast acquisition time and low phase jitter

A first-order digital phase locked loop (DPLL) is presented. The phase error is accumulated and averaged over a number of cycles of the DPLL output, which in turn determines the number of pulses inserted/deleted from a high-frequency clock. The optimum number of cycles of the DPLL output used for averaging are determined for the acquisition and steady-state modes. For fast acquisition the number of output cycles used for phase error averaging is small, and during the steady-state mode a larger value is chosen to minimize the output phase error. The theoretical results are verified by computer simulation, and the performance of the DPLL is compared with that of some other well-known DPLLs