DocumentCode :
1696683
Title :
Designing Large Hierarchical Multiprocessor Systems under Processor, Interconnection, and Packaging Advancements
Author :
Basak, Debashis ; Panda, Dhabaleswar K.
Author_Institution :
The Ohio State University, USA
Volume :
1
fYear :
1994
Firstpage :
63
Lastpage :
66
Abstract :
A general framework for architectural design of large hierarchical multiprocessor systems under rapidly changing packaging, processor, and interconnection technologies is presented. In recent years processor boards with larger area (A) and greater pinouts are becoming feasible. Board interconnection technology has advanced from peripheral connections O(sqrt A ) to elastomeric surface connections 0(A). As processor and interconnection technology grows, there is a varying demand on the interconnection network of the system. The proposed framework is capable of taking into account all these changes in technologies and, depending on a given set of technological parameters, derive the most optimum topology. The framework is illustrated by considering the design problem of the currently popular class of k-ary n-cube cluster-c scalable architectures.
Keywords :
Concurrent computing; Costs; Guidelines; Information science; Multiprocessing systems; Multiprocessor interconnection networks; Network topology; Packaging machines; Parallel processing; Process design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Processing, 1994. Vol. 1. ICPP 1994. International Conference on
Conference_Location :
North Carolina State University, NC, USA
ISSN :
0190-3918
Print_ISBN :
0-8493-2493-9
Type :
conf
DOI :
10.1109/ICPP.1994.88
Filename :
4115694
Link To Document :
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