DocumentCode :
1696716
Title :
System-on-chip design with dataflow architecture
Author :
Wu, Baifeng ; Peng, Chenglian
Author_Institution :
Fudan Univ., Shanghai, China
Volume :
2
fYear :
2004
Firstpage :
712
Abstract :
This work presents a practical approach to implement dataflow dominated system-on-chip system with real-time requirements. With dataflow model and a virtual component (VC)-oriented implementation architecture, the approach has the advantages of effectively supporting design reuse or reconfiguration. Single bus architecture reduces the design complexity and implementation cost and provides an effective way to meet real-time constraints. Based on the architecture some important aspects such as bus arbitrating, VC framework are described, these techniques are critical factors for achieving design goal.
Keywords :
data flow graphs; integrated circuit design; microprocessor chips; parallel architectures; real-time systems; system-on-chip; a virtual component-oriented implementation architecture; bus arbitration; dataflow architecture; dataflow model; design complexity; design reconfiguration; design reuse; real-time constraints; real-time requirements; single bus architecture; system-on-chip design; Computational modeling; Data flow computing; Decoding; Design methodology; Embedded system; Process design; Real time systems; System-on-a-chip; Timing; Virtual colonoscopy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Supported Cooperative Work in Design, 2004. Proceedings. The 8th International Conference on
Print_ISBN :
0-7803-7941-1
Type :
conf
DOI :
10.1109/CACWD.2004.1349283
Filename :
1349283
Link To Document :
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