An 18-34 GHz dynamic frequency divider based on 0.2 mu m AlGaAs/GaAs/AlGaAs quantum-well transistors

The design and performance of a dynamic frequency divider operating in the 18-34-GHz range are presented. The schematic of the dynamic frequency divider is shown. Two ring oscillators, each consisting of one SBFL inverter and two source followers, are fed back by transfer gates. A memory type flip-flop is used for data storage during the period when the transfer gates show high resistance due to the low voltage applied to the clock input. The circuit design is optimized by SPICE simulation on the basis of a HEMT (high electron mobility transistor) network model. Measurements on the frequency divider give an 18-GHz lower limit for stable operation. 34 GHz is measured for the maximum input frequency. The pulse diagram of the 34-GHz input and the 17-GHz output is shown.<>